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Posted: Monday, March 13, 2017 6:03 PM

Req Id: 74561
As an Emerging memory Physical Design Engineer in Microns Technology Development (R and D) organization, you will implement the layout and run the layout verification flows including LVS, DRC, ESD, Latch:up, Density Check, etc. for large scale custom design projects that will include both Analog and Digital circuits. In addition to the layout and verification of the circuits, you will also be responsible for floor planning the full chip and supervising the floor planning of the sub blocks of the chip. Additionallyresponsibilities includeassembling the full chip and preparing the full chip database for Mask Generation.
Job Responsibilities:
:Must have strong skills in custom layout, floor planning, matching techniques and manual routing
:Be able to learn and understand design rules and deliver quality layout
:Understanding of layout methodology from initial chip plan to tapeout
:Strong debug and problem:solving skills for LVS, DRC and layout issues without much supervision
:Experience with Cadence tool, VXL, Calibre tool
:Independent with strong analytical skills, creative thinking and self:motivated
:The position requires an individual with the ability to learn rapidly and adapt quickly to changing situations
:Layout experience with memory array is plus
Successful candidates for this position will have
:Strong communication skills
:Strong leadership skills
:Experience coordinating and supervising the work of others.
:Experience in layout design on non:volatile memory
:Familiarity with CAD and EDA tools including Cadence Virtuoso, Calibre and Hercules.
:Knowledge of programming languages like Perl, Skill and Shell scripting.
Associates Degree with 3:5 years of experience or Bachelors/Masters Degree in Electrical Engineering.
We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a persons race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran's status, or other classifications protected under law. This includes providing reasonable accommodation for team members disabilities or religious beliefs and practices.
Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.
To request assistance with the application process, Micron's Human Resources Department at (or
Keywords: Folsom California (US:CA) United States (US) RD Experienced Regular Engineering *LI:KV1


• Location: folsom, Sacramento

• Post ID: 13745972 sacramento is an interactive computer service that enables access by multiple users and should not be treated as the publisher or speaker of any information provided by another information content provider. © 2017