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Posted: Wednesday, March 7, 2018 9:26 AM

The successful candidate will work as a senior member of the pre-silicon verification team for the CSME Converged Security and Manageability Engine, Innovation Engine IE and related IP blocks.

  • Architects and develops Pre-Silicon functional validation collateral to verify system will meet design requirements
  • Creates and executes test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests
  • Analyzes and uses results to modify testing

The responsibilities will include but not be limited to:

  • Defining, implementing, and deploying verification capabilities, methodologies, and process improvements
  • Development and execution of test-plans, test-bench components BFMs, checkers, trackers, scoreboards and functional coverage
  • Working closely with other verification engineers, RTL design engineers, micro-architects, and other team members to ensure quality of test-plans, verification environment, and tests
  • Strong discipline and attention to detail in ensuring high quality verification that minimizes bug escapes to higher levels of validation
  • Mentorship of junior team members on verification BKMs and debug


Minimum Qualifications:

  • MS in EE/CS and 3+ years of relevant experience
  • Extensive experience with architecting verification environments and components random test generators, scoreboards, BFM's, coverage, etc.
  • Proven knowledge of System Verilog, OVM/UVM, object-oriented programming
  • Strong understanding of logic design and micro-architecture fundamentals
  • Must demonstrate strong initiative, teamwork, planning, and communication abilities due to deliverables impacting multiple projects and stakeholders
  • Excellent verbal and written communications skills

Preferred Qualifications:

  • Knowledge of C/C++ & Perl scripting preferred
  • Strong knowledge of SIP tools and methodologies like Saola, ACE, VCS, etc.
  • Knowledge of standard bus protocols like PCI, IOSF, AHB, etc. is highly preferred

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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• Location: Sacramento

• Post ID: 22398362 sacramento is an interactive computer service that enables access by multiple users and should not be treated as the publisher or speaker of any information provided by another information content provider. © 2018